Active matrix display devices in which a switching element is formed for each pixel to achieve a high-definition display in liquid crystal display devices are publicly known and organic electroluminescence display devices have recently attracted a great deal of attention.
FIGS. 1A–1I are cross sectional views illustrating the steps of manufacturing an active matrix liquid crystal display device according to a related art.
Step A (FIG. 1A): On an insulating substrate 310, an amorphous silicon (hereinafter referred to as “a-Si”) film 320 is formed.
Step B (FIG. 1B): A surface of the a-Si film 320 is irradiated with beams of focused laser light (laser beams) to melt and recrystallize a-Si, thereby forming a polysilicon (hereinafter referred to as “poli-Si”) film. Through photolithography and etching, the poli-Si film is patterned as an island, thereby forming a semiconductor film 330.
Step C (FIG. 1C): On the insulating substrate 310 and the semiconductor film 330, a gate insulating film 340 is formed of an SiO2film as a first insulating film. On the gate insulating film 340, a metal film of chromium (Cr) is formed, and through photolithography and etching a gate electrode 350 is formed on the gate insulating film 340 at a position corresponding to and located over a central portion of the semiconductor film 330.
Step D (FIG. 1D): P-type or N-type impurities are doped to the semiconductor film 330 using the gate electrode 350 as a mask. A heat treatment is performed to activate the doped impurities, thereby forming a source region 330a and a drain region 330b in the semiconductor film 330.
Thus, a poli-Si TFT, which is a semiconductor element, is formed.
Step E (FIG. 1E): On the gate insulating film 340 and the gate electrode 350, a two-layered interlayer insulating film 360 composed of an SiO2 film 360a and an SiN film 360b is formed as a second insulating film.
Step F (FIG. 1F): A plurality of first contact holes 370 are formed penetrating the gate insulating film 340 and the interlayer insulating film 360 to expose the source region 330a and the drain region 330b. In the first contact hole 370 exposing the drain region 330b, wiring 380 is formed of aluminum (Al) extending in a direction perpendicular to the plane of the sheet.
Step G (FIG. 1G): A planarization film 390 is formed of an organic type material on the noted first contact hole 370, the interlayer insulating film 360, and the wiring 380, thereby planarizing the surface.
Step H (FIG. 1H): A second contact hole is formed penetrating the planarization film 390 and exposing the source region 330a. In this second contact hole, a pixel electrode 400 is formed of ITO (indium tin oxide) connected to the source region 330a and spreading over the planarization film 390.
Step I (FIG. 1I): An alignment film 410 for alignment of liquid crystal is formed of polyimide, SiO2, or the like on the pixel electrode 400 and the planarization film 390.
A TFT substrate of the active matrix liquid crystal display device is thus formed. The liquid crystal display device is formed by liquid crystal sandwiched by the TFT substrate and an opposite substrate having a common electrode formed thereon.
According to the above-described manufacturing method, the second contact hole connecting the source region 330a of the TFT and the pixel electrode 400 is formed penetrating the planarization film 390 and the interlayer insulating film 360, and is therefore relatively deep compared to the diameter of the opening, i.e. it has a large aspect ratio. As a result, the planarization film 390 may not be completely removed to reach the source region 330a for forming the second contact hole. On the other hand, when etching is performed for a longer period of time in order to completely remove the planarization film 390, a completely selective etching cannot be performed between the planarization film 390 and the interlayer insulating film 360 and the semiconductor film 330, giving rise to a rough surface of the source region 330a of the semiconductor film 330. Thus, etching adjustment is difficult and errors in depth or size of the contact holes are common, which adversely affects yield.
In addition, because the contact hole is formed through etching utilizing chemical reaction, the area of the contact hole at an upper end exceeds that at the bottom surface. The difference increases as the hole becomes deeper, and therefore a large area is required at the upper end for forming a deep contact hole, preventing enhancement of integration level.
The present invention has been conceived in view of the above-described problems, with the aim of making possible easy and reliable fabrication of a contact hole and achieving increased yields and further enhancement of the integration level.
Another object of the present invention is to prevent curing of a mask material during impurity doping for manufacturing a thin film transistor.